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How Do Internal Reorderings in C Atomic Read-Modify-Write Operations Affect Memory Ordering?
How Do Internal Reorderings in C Atomic Read-Modify-Write Operations Affect Memory Ordering?
Dec 09, 2024 pm 07:59 PM
Treatment of Atomic Read-Modify-Write (RMW) Operations in Memory Ordering
In response to the question regarding the nature of atomic read-modify-write (RMW) operations, the C standard classifies them as single operations with semantics that combine both acquire and release properties.
Implications for Ordering
This designation implies that no memory reads or writes occurring in the same thread can be reordered before or after an RMW operation. However, it does not preclude the possibility of reordering between the internal read and write components of the RMW.
Concrete Example
Consider the code example provided:
std::atomic<int> x, y;
void thread_A() {
x.exchange(1, std::memory_order_acq_rel);
y.store(1, std::memory_order_relaxed);
}
void thread_B() {
int yy = y.load(std::memory_order_acquire);
int xx = x.load(std::memory_order_acquire);
std::cout << xx << ", " << yy << std::endl;
}
In this scenario, Thread B can indeed output 0, 1. This is because the load and store operations performed within Thread A's RMW operation can be internallyreordered, allowing Thread B to observe the state after the load (0) but before the store (1).
ARM64 Implementation
The ARM64 implementation of the RMW operation, as described by the ldaxr, stlxr, and str instructions, aligns with the standard's expectations. The str instruction can be visible before the stlxr instruction, potentially leading to the observation of 0, 1 by Thread B.
Memory Order Implications
Replacing memory_order_acq_rel with seq_cst would not affect this behavior, as it only introduces additional semantics relative to other seq_cst operations, which are not present in the code example.
Conclusion
Atomic RMW operations in C are singular operations with acquire-release semantics. While they prevent reordering of external operations before and after, the potential for reordering between their internal components allows for scenarios like the one in the code example, where Thread B can output 0, 1.
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